This application relates to semiconductor structures and methods for forming and operating the semiconductor structures and more particularly to Flash cell structures, array structures and methods for operating the Flash array structures.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
FIG. 1 is a cross-sectional view of a traditional EEPROM cell structure. In FIG. 1, select transistor 110 is adjacent to memory cell 120 to constitute a cell unit. Select transistor 110 has source 101 and common source 103 formed within substrate 100. Gate oxide layer 111 and select gate 113 are formed over substrate 100. Memory cell 120 has common source 103 and drain 105. Tunneling oxide layer 121, floating gate 122, oxide layer 123/nitride layer 124/oxide layer 125 (ONO), and gate 126 are sequentially formed over substrate 100. Select transistor 110 is configured to control the operations of memory cell 120.
In a traditional channel hot electron programming method, select transistor 110 is turned on. Source 101 is ground. Drain 105 is coupled to a 4-5V power. 8-10V is applied to gate 126, such that hot electrons are injected into floating gate 122.
In a traditional source-side FN erasing method, select transistor 110 is turned on. Source 101 is coupled to a 5V power. Drain 105 is floating. −10V is applied to gate 126, such that electrons are pulled into common source 103 from floating gate 122.
In a traditional channel FN erasing method, source 101 is floating. Substrate 100 is coupled to a 6-8V power. Drain 105 is floating. −8V is applied to gate 126, such that electrons are pulled into substrate 100 from floating gate 122.
In a traditional read method, select transistor 110 is turned on. Source 101 is ground. Drain 105 is coupled to a 0.6V power. 5V is applied to gate 126 so as to determine the state of memory cell 120.
In a traditional memory cell having a so-called SONOS (silicon-oxide-nitride-oxide-silicon) structure, the nitride layer serves as a charge storage layer (not shown). In a traditional channel hot electron programming method for SONOS cell, a select transistor is turned on. A source is ground. A drain is coupled to a 5V power. 10V is applied to a gate of the SONOS memory cell, such that hot electrons are injected into the charge storage layer.
In a traditional band-to-band erase method for SONOS cell, a select transistor is turned off. A source is floating. A substrate is grounded. A drain is coupled to a 5V power. −10V is applied to a gate of the SONOS memory cell, such that hot holes are injected into the charge storage layer and combine with trapped electrons.
In a traditional read method for SONOS cell, a select transistor is turned on. A source is grounded. The drain is coupled to a 0.6V power. 5V is applied to a gate of the SONOS memory cell so as to determine the state of the SONOS memory cell.